Our research is focused on integrated systems and circuits, with applications in the area of optoelectronics, high-speed interconnects, wireless systems, and edge computing. As such, we are often investigating challenges that fall at the intersection of circuits and communication systems, photonics, physics, quantum mechanics, signal processing, computing and machine learning.
Major Research Thrusts:
Frequency Synthesizers for Massive MIMO:
Massive multiple-input multiple-output (Ma-MIMO) architectures require large-scale arrays of transmitter, receivers and clocking circuits to co-exist and cooperate in order to attain the increased network capacity for next-generation wireless networks. New design techniques are needed to aggressively scale down the area and power consumption of these circuits to realize such large-scale arrays.
A survey of CMOS phase locked loops (PLLs) over the last two decades show that the overall performance of PLL based frequency synthesizers are bounded by a tradeoff between noise, area and power consumption. Analog Type-II PLLs are very popular due to their low noise performance, but are area and power hungry. All-digital PLLs are compact and friendly to technology scaling, but limited in noise performance under a restrained power budget.
Our research is focused on using Type-I PLL to ease the tradeoffs, and achieve good noise performance in a compact footprint and low power budget. Overcoming the limitations of conventional Type-I topologies, our recent voltage-mode prototype demonstrated comparable performance to start-of-the-art architectures, but in an area of only 0.12 mm2 in 0.13-μm CMOS [SharkiaCICC15, SharkiaTCAS18]. This was followed by a sub-sampling Type-I architecture that achieved the best-reported noise-power figure of merit (FoM) in an area of 100µm x 100µm, thus proving for the first time that an LC PLL can beat the state-of-the-art power-performance benchmarks with an area of a ring-based PLL [SharkiaISSCC18, SharkiaJSSC18].
Majority of optoelectronics links in datacenters employ 850 nm wavelength VCSELs and photodetectors (PDs) for interconnects spanning a length of few meters up to 300 m [AhmedJSTQE16]. With newer standards focusing on higher data rates and advanced modulation schemes such as pulse amplitude modulation (PAM4), effects such as reliability, bondwires, linearity and crosstalk must be carefully addressed in the system design for an energy-efficient link design. We recently presented a differential push-pull voltage-mode VCSEL driver and demonstrated that it mitigates the challenges of high power consumption, sensitivity to packaging and incompatibility to advanced CMOS process scaling. Our prototype has achieved the highest ever-reported power conversion efficiency for VCSEL drivers when normalized to VCSEL slope efficiency [RamaniTCAS19]. At the receiver (RX) side, we have recently demonstrated a monolithically integrated Avalanche Photodetectors and transimpedance amplifier (TIA) in a standard 0.13um CMOS process. Fully monolithic integration relaxes many challenges associated with traditional APDs. The RX achieved a sensitivity of -18.8 dBm, the best-reported among 10 Gb/s linear CMOS TIAs operating at 850 nm [NayakTCAS19].
Silicon photonics has now emerged as a potential disruptive technology for meeting the bandwidth requirements of medium-to-long reach interconnects for datacenters. Derived from the mature CMOS fabrication technology, silicon photonics fabrication provides a platform where optical signals can be efficiently manipulated at large scales using inexpensive and densely integrated components on-chip. Our research efforts include design of high-speed drivers and transimpedance amplifiers for various modulation schemes such as NRZ/PAM4/QPSK/QAM. Our recent work on coherent silicon photonic links, in collaboration with Elenion, remains the fastest link published to date on a silicon platform, demonstrating a data rate of > 0.5 Tb/s/wavelength [AhmedISSCC19].
Practical Deployment of Silicon Ring Resonator Systems
By confining light into resonant structures of um2-scale sizes, microring resonators (MRRs) on silicon photonic platforms allows for low-power, dense, and large-scale manipulation of optical signals on-chip. As a result, MRR-based modulators, switches, and filters bear the promise to be the key building blocks in integrated optical circuits for applications in future data communications, high-performance computing, neuromorphic photonics and sensing. MRR-based modulators promise highly efficient transceivers for datacenters [AhmedJSTQE16, ShomanOFC18]. However, temperature and fabrication variations cause significant shifts in the MRR’s spectral responses, degrading their performance. Conventional solutions to tune MRR require complicated control electronics and several contact pads around MRR, increasing their effective area. These challenges have plagued the widespread adoption of MRR systems beyond the academic world.
We have introduced in-resonator photoconductive heaters (IRPHs) as compact, low-cost implementations to simultaneously sense and tune the resonance conditions of MRRs, without requiring additional material depositions. We have demonstrated automatic tuning and stabilization of one- and two-ring filters [JayatillekaOFC16, JayatillekaOpEx15], four-ring Vernier filters [JayatillekaOFC17, JayatillekaJLT17], and higher-order coupled-optical-resonator-waveguides (CROWs), using simple algorithms. These include record tuning demonstrations for 37.6 nm wavelength range and 65 oC temperature variation. Recently, we demonstrated some of the most complex and largest MRR systems [Jayatilleka-ShomanOptica19].
We have also recently demonstrated a compact microring modulator with tunable extinction ratio to compensate for fabrication uncertainties [ShomanOFC18].
CMOS Clocking for mm-wave Applications
The deployment of mm-wave portion of frequency spectrum (30 GHz to 300 GHz) for wireless applications is gaining tremendous popularity. The availability of wide bandwidth at the lower mm-wave bands (near 30 GHz, 60 GHz, etc.) makes these bands attractive for next generation mobile network. A key challenge in most CMOS communication systems operating at these bands is synthesis of on-chip LO frequency – with high spectral purity and large tuning range.
The upper mm-wave (200GHz and higher) and sub-THz bands are also attractive for applications such as medical imaging, non-invasive industrial testing and spectroscopy. Although CMOS promises a low-cost, portable platform for these applications, efficient power generation at these high frequencies faces daunting challenges on several fronts.
Our recent work has focused on using harmonics, mixing and multiplications for mm-wave clock generation in bulk CMOS processes. These include some of the most efficient and low-noise CMOS oscillators at ~30 GHz [LightbodyRFIC18], 60 GHz [ShiraziJSSC16], 225 GHz [NikpaikJSSC17] and 300 GHz [ShiraziRFIC16].
Simultaneous Full-Duplex Radios:
In wireless transceivers, transmitter (TX) and receiver (RX) either share the same frequency band but operate in different time slots (TDD), or share the same time slot but operate in different frequency bands (FDD). A commercial, simultaneous full-duplex (FD) radio sharing identical time slots and frequency bands for the TX/RX pair is still be to realized because of the self-interference (SI) from the TX that is several orders of magnitude stronger than the desired signal at the RX. Realizing such SI cancellation has been hitherto very challenging, because not only does it demand broadband cancellation in amplitude, phase and group delay of the echo signals, but also require such a cancellation circuit to be linear, low-noise and ultra-compact for a mobile form factor.
We recently demonstrated a self-interference cancellation IC with a record bandwidth of 80 MHz for a linear, tunable, compact, and fully-integrated FD implementation [ElSayedRFIC16, ElSayedTCAS19]. Utilizing techniques such as frequency translations and Hilbert transforms, up to 23 dB of SI cancellation is achieved in an active area of just 0.84 mm2.
High-speed Input/Output (I/O) data links are used to communicate between microprocessor, memory, hard drive, external plug-and-play devices, etc. Our group is currently investigating low-power links for accelerators and silicon interposer applications, as well as high-performance supporting PAM4 and other advanced modulation schemes. More details and results coming soon….
Deep Learning for Edge Devices:
The Internet of Thing (IoT) industry is experiencing an explosive growth with applications like personal area networks, industrial and agricultural sensor networks becoming widespread. One major challenge for these network is handling the massive amount of data that they capture and must transmit back to the base station. If apart from sensing, if these devices become smart in learning and inference, it will accelerate the adoption of IoT tremendously. Recently, with the drive towards system-on-chip (SOC) integration, there has been a tremendous interest in implementing digital and mixed signal circuits in CMOS technology to implement machine learning techniques such as deep learning. Low latency, area and power consumption without compromising accuracy are some of the key design concerns that our group is currently investigating for the hardware implementation for such edge devices.