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**Journals**

78. A. Ahmedu, L. Vera, R. Shi, L. Lotti, S. Shekhar, and A. Rylyakov, “A dual-polarization silicon-photonic coherent receiver front-end supporting 528 Gb/s/wavelength,” IEEE J. Solid-State Circuits, Mar. 2023 (accepted, early access).

77. A. Mishrau, Y. Li, P. Agarwal, and S. Shekhar, “Improving Linearity in CMOS Phase Interpolators,” IEEE J. Solid-State Circuits, Feb. 2023 (accepted, early access).

76. L. Diasu, H. Shomanu, E. Luan, H. Jayatillekau, S. Shekhar, L. Chrostowski, and N. Jaeger, “Cost effective silicon-photonic biosensors using doped silicon detectors and a broadband source,” Optics Express, Feb. 2023 (accepted, early access).

75. H. Abolmagd, R. Subbaraman, O. Esmaeeli, Y. Guntupalli, A. Sharkia, D. Bharadia, and S. Shekhar, “A hierarchical self-interference canceller for full-duplex LPWAN applications achieving 52–70-db RF cancellation”, *IEEE Journal of Solid-State Circuits*, vol. , no. , pp. 1–14, 2022.

74. S. Nezami *et al*., “Packaging and Interconnect Considerations in Neuromorphic Photonic Accelerators“, in *IEEE Journal of Selected Topics in Quantum Electronics*, vol. 29, no. 2, pp. 1-11, 2023. [PDF]

73. Z. Guo *et al*., “Multi-Level Encoding and Decoding in a Scalable Photonic Tensor Processor With a Photonic General Matrix Multiply (GeMM) Compiler“, in *IEEE Journal of Selected Topics in Quantum Electronics*, vol. 28, no. 6, pp. 1-14, 2022. [PDF]

72. L. S. Puumala, S. M. Grist, K. Wickremasinghe, M. A. Al-Qadasi, S. J. Chowdhury, Y. Liu, M. Mitchell, L. Chrostowski, S. Shekhar, and K. C. Cheung, “An optimization framework for silicon photonic evanescent-field biosensors using sub-wavelength gratings”, *Biosensors*, vol. 12, no. 10, pp. 840, 2022. [PDF]

71. I. Taghavi, M. Moridsadat, A. Tofini, S. Raza, N. A. Jaeger, L. Chrostowski, B. J. Shastri, and S. Shekhar, “Polymer modulators in Silicon Photonics: Review and Projections”, *Nanophotonics*, vol. 11, no. 17, pp. 3855–3871, 2022. [PDF]

70. B. J. Shastri, M. J. Filipovich, Z. Guo, P. R. Prucnal, S. Shekhar and V. J. Sorger, “In situ training with silicon photonics neural networks“, *2022 Photonics North (PN)*, vol. , no. ,pp. 1-2, 2022.

69. A. Ghorbani-Nejad, A. Nikpaik, A. Nabavi, A. H. Masnadi Shirazi, S. Mirabbasi and S. Shekhar, “Optimum Conditions for Efficient Second-Harmonic Power Generation in mm-Wave Harmonic Oscillators“, in *IEEE Journal of Solid-State Circuits*, vol. 57, no. 7, pp. 2130-2142, 2022.

68. J. Singh, H. Morison, Z. Guo, B. A. Marquez, O. Esmaeeli, P. R. Prucnal, L. Chrostowski, S. Shekhar, and B. J. Shastri, “Neuromorphic photonic circuit modeling in Verilog-A”, *APL Photonics*, vol. 7, no. 4, pp. 046103, 2022. [PDF]

67. O. Esmaeeli *et al*., “A Transformer-Based Technique to Improve Tuning Range and Phase Noise of a 20–28GHz LCVCO and a 51–62GHz Self-Mixing LCVCO“, in *IEEE Transactions on Circuits and Systems I: Regular Papers*, vol. 69, no. 6, pp. 2351-2363, 2022.

66. I. Taghavi, R. Dehghannasiri, T. Fan, A. Tofini, H. Moradinejad, A. A. Efterkhar, S. Shekhar, L. Chrostowski, N. A. F. Jaeger, and A. Adibi, “Enhanced polling and infiltration for highly efficient electro-optic polymer-based Mach-Zehnder modulators“, *arXiv preprint*, vol. , no. , 2022. [PDF]

65. A. K. Mishra, Y. Li, P. Agarwal and S. Shekhar, “A 9b-Linear 14GHz Integrating-Mode Phase Interpolator in 5nm FinFET Process“, *2022 IEEE International Solid- State Circuits Conference (ISSCC)*, vol. , no. , pp. 1-3, 2022.

64. M. A. Al-Qadasi, L. Chrostowski, B. J. Shastri, and S. Shekhar, “Scaling up silicon photonic-based accelerators: Challenges and opportunities”, *APL Photonics*, vol. 7, no. 2, pp. 020902, 2022. [PDF]

63. H. Abolmagd, R. Subbaraman, O. Esmaeeli, Y. Guntupalli, A. Sharkia, D. Bharadia, and S. Shekhar, “A hierarchical self-interference canceller for full-duplex LPWAN applications achieving 52–70-db RF cancellation”, *IEEE Journal of Solid-State Circuits*, vol. , no. , pp. 1–14, 2022.

62. C. Huang et al., “Prospects and applications of photonic neural networks”, *Advances in Physics: X* 7, no. 1, pp.1981155, 2022. [PDF]

61. Z. Guo *et al*., “Multi-level Encoding and Decoding in a Wavelength-Multiplexed Photonic Tensor Processor“, *2021 IEEE 17th International Conference on Group IV Photonics (GFP)*, vol. , no. , pp. 1-2, 2021. [PDF]

60. M. J. Filipovich et al., “Monolithic silicon photonic architecture for training deep neural networks with direct feedback alignment“, *arXiv preprint *arXiv:2111.06862, vol. , no. , pp. , 2021. [PDF]

59. V. Suntharalingam and S. Shekhar, “Guest Editorial Introduction to the Special Issue on the 2021 IEEE International Solid-State Circuits Conference (ISSCC)“, in *IEEE Journal of Solid-State Circuits*, vol. 56, no. 11, pp. 3207-3208, 2021.

58. H. Shoman *et al*., “Stable and Reduced-Linewidth Laser Through Active Cancellation of Reflections Without a Magneto-Optic Isolator“, in *Journal of Lightwave Technology*, vol. 39, no. 19, pp. 6215-6230, 2021. [PDF]

57. M. A. AI-Qadasi, L. Chrostowski, B. J. Shastri, and S. Shekhar, “Scaling up silicon photonic-based accelerators: challenges and opportunities, and roadmapping with silicon photonics 2.0”, *arXiv preprint arXiv:2109.08025*, vol. , no. , pp. , 2021. [PDF]

56. H. Shoman et al., “Stable Laser Without a Magneto-optic Isolator“, *2021 European Conference on Optical Communication (ECOC),* vol. , no. , pp. 1-4, 2021.https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=9605978

55. S. Shekhar, “Silicon Photonics: A brief tutorial“, in *IEEE Solid-State Circuits Magazine*, vol. 13, no. 3, pp. 22-32, 2021.

54. A. E. Afifi, S. Shekhar, J. F. Young and L. Chrostowski, “Integrated Contra-directional Pump-reject Filters for Photon-pair Sources in Silicon“, *2021 Conference on Lasers and Electro-Optics (CLEO)*, pp. 1-2, 2021.

53. J. Shastri *et al*., “Silicon Photonics for Artificial Intelligence and Neuromorphic Computing“, *2021 IEEE Photonics Society Summer Topicals Meeting Series (SUM)*, vol. , no. , pp. 1-2, 2021. [PDF]

52. B. J. Shastri *et al*., “Neuromorphic Photonic Networks“, *2021 Optical Fiber Communications Conference and Exhibition (OFC)*, vol. , no. , pp. 1-2, 2021. [PDF]

51. A. E. Afifi, S. Shekhar, J. F. Young and L. Chrostowski, “Integrated Contra-directional Pump-reject Filters for Photon-pair Sources in Silicon“, *2021 Conference on Lasers and Electro-Optics (CLEO)*, vol. , no. , pp. 1-2, 2021.

50. B. A. Marquez et al., “On-chip online learning and inference for photonic pattern recognition“, *2021 Conference on Lasers and Electro-Optics (CLEO),* vol. , no. , pp. 1-2, 2021. [PDF]

49. C. Mosquera, H. Shoman, S. Shekhar, and L. Chrostowski, “Compact model of in-waveguide silicon photoconductive heater-detectors for tuning photonic circuits”, *Silicon Photonics XVI*, vol. , no. , pp. , 2021. [PDF]

48. L. Chrostowski, D. Leanne, M. Matthew, M. Connor, E. Luan, M. Al-Qadasi, R. Avineet, H. R. Mojaver, E. Lyall, A. Gervais, R. Dubé-Demers, K. M. Awan, S. Gou, O. Liboiron-Ladouceur, W. Shi, S. Shekhar, and K. Cheung, “A silicon photonic evanescent-field sensor architecture using a fixed-wavelength laser”, *Optical Interconnects XXI*, vol. , no. , pp. , 2021. [PDF]

47. A. Marquez, Z. Guo, H. Morison, S. Shekhar, L. Chrostowski, P. Prucnal, and B. J. Shastri, “Photonic pattern reconstruction enabled by on-chip online learning and inference”, *Journal of Physics: Photonics*, vol. 3, no. 2, p. 024006, 2021. [PDF]

46. A. Mukherjee, K. Saurav, P. Nair, S. Shekhar and M. Lis, “A Case for Emerging Memories in DNN Accelerators“, *2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)*, vol. , no. , pp. 938-941, 2021. [PDF]

45. T. C. Carusone, S. Shekhar, Y. Frans, W.-Z. Chen, T. Toifl, M. Nagatani, F. Dielacher, and W. Redman-White, “F6: Optical and electrical transceivers for 400GbE and Beyond”, *2021 IEEE International Solid- State Circuits Conference (ISSCC)*, vol. , no. , pp. , 2021.

44. A. K. Mishra, S. Aniruddhan and S. Shekhar, “Injection Locking in Switching Power Amplifiers“, in *IEEE Access*, vol. 8, no. , pp. 167555-167569, 2020. [PDF]

43. M. Ma, H. Shoman, S. Shekhar, N. A. F. Jaeger and L. Chrostowski, “Automated Adaptation and Stabilization of a Tunable WDM Polarization-Independent Receiver on Active Silicon Photonic Platform“, in *IEEE Photonics Journal*, vol. 12, no. 4, pp. 1-11, 2020. [PDF]

42. M. Ma, H. Shoman, S. Shekhar, N. A. F. Jaeger and L. Chrostowski, “Silicon Photonic WDM-Polarization Receiver with Automated Feedback Control“, *2020 Conference on Lasers and Electro-Optics (CLEO),* vol. , no. , pp. 1-2, 2020.

41. H. Shoman, H. Jayatilleka, N. A. F. Jaeger, S. Shekhar and L. Chrostowski, “A Single Microring Resonator for Measuring Waveguide Losses“, *2020 Conference on Lasers and Electro-Optics (CLEO),* vol. , no. , pp. 1-2, 2020. [PDF]

40. A. H. Ahmed, A. El Moznine, D. Lim, Y. Ma, A. Rylyakov, and S. Shekhar, “A dual-polarization silicon-photonic coherent transmitter supporting 552 Gb/s/wavelength”, *IEEE J. Solid-State Circuits*, vol. , no. , pp. 1-11, 2020 (Early Access).

39. E. Ghaderi, A. Ramani, A. Rahimi, D. Heo, S. Shekhar and S. Gupta, “Four-element wide modulated bandwidth MIMO receiver with> 35-dB interference cancellation”, *IEEE Trans. Microwave Theory Techniques*, vol. , no. , pp. 1-1, 2020 (Early Access). [PDF]

38. H. Shoman, H. Jayatilleka, N. Jaeger, S. Shekhar, and L. Chrostowski, “Measuring on-chip waveguide losses using a single, two-point coupled microring resonator”, *Optics Express*, vol. 28, no. 7, pp. 10225-10238, Mar. 2020.

37. C. Yuan, A. Naguib and S. Shekhar, “On the design of low-power hybrids for full duplex simultaneous bidirectional signaling links”, *IEEE Trans. Circuits and Systems – I*, vol. 67, no. 4, pp. 1413-1422, Apr. 2020.

36. M. Ma, H. Shoman, K. Tang, S. Shekhar, N. Jaeger, and L. Chrostowski, “Automated control algorithms for silicon photonic polarization receiver”, *Optics Express*, vol. 28, no. 2, pp. 1885-1896, Jan. 2020. [PDF]

35. A. Ramani, S. Nayak and S. Shekhar, “A differential push-pull voltage mode VCSEL driver in 65-nm CMOS”, *IEEE Trans. Circuits and Systems – I*, vol. 66, no. 11, pp. 4147-4157, Nov. 2019.

34. H. Shoman, H. Jayatilleka, A. H. K. Park, A. Mistry, N. A. F. Jaeger, S. Shekhar, and L. Chrostowski, “Compact wavelength- and bandwidth-tunable microring modulator”, *Optics Express*, vol. 27, no. 19, pp. 26661-26675, Sep. 2019. [PDF]

33. C. Yuan and S. Shekhar, “A supply-noise-insensitive digitally-controlled-oscillator”, *IEEE Trans. Circuits and Systems – I*, vol. 66, no. 9, pp. 3414-3422, Sep. 2019.

32. E. Ghaderi, A. Ramani, A. Rahimi, D. Heo, S. Shekhar and S. Gupta, “An integrated discrete-time delay-compensating technique for wide-band large array beamformers”, *IEEE Trans. Circuits and Systems – I*, vol. 26, no. 9, pp. 3296-3306, Sep. 2019.

31. L. Chrostowski, H. Shomanu, M. Hammood, J. Jhoja, E. Luan, S. Lin, A. Mistry, D. Witt, N. A. F. Jaeger, S. Shekhar, H. Jayatillekau, P. Jean, S. B. deVillers, J. Cauchon, W. Shi, C. Horvath, J. N. Westwood-Bachman, K. Setzer, M. Aktary, N. S. Patrick, R. Bojko, A. Khavasi, X. Wang, T. Lima, A. Tait, P. Prucnal, D. E. Hagan, D. Stevanovic, A. P. Knights, “Silicon photonic circuit design using rapid prototyping foundry process design kits”, *IEEE J. Sel. Topics Quant. Electron. *, vol. 25, no. 5, pp. 1-26, Sep. 2019 (invited).

30. M. AlTaha, H. Jayatilleka, Z. Lu, J. Chung, D. Celo, D. Goodwill, E. Bernier, S. Mirabbasi, L. Chrostowski, and S. Shekhar, “Monitoring and automatic tuning and stabilization of a 2×2 MZI optical switch for large-scale WDM switch networks”, *Optics Express*, vol. 27, no. 17, pp. 24747-24764, Aug. 2019. [PDF]

29. S. Nayak, A. Ahmed, A. Sharkia, A. Ramani, S. Mirabbasi, and S. Shekhar, “A 10-Gb/s –18.8 dBm sensitivity 5.7 mW fully-integrated optoelectronic receiver with on-chip avalanche photodetector in 0.13-um CMOS”, *IEEE Trans. Circuits and Systems – I*, vol. 66, no. 8, pp. 3162-3173, Aug. 2019. [PDF]

28. S. Shekhar, R. Inti, J. E. Jaussi, T-C. Hsueh, and B. Casper, “A low-power bidirectional link with a direct data-sequencing blind oversampling CDR”, *IEEE J. Solid-State Circuits*, vol. 54, no. 6, pp. 1669-1681, June 2019.

27. A. Park, H. Shoman, M. Ma, S. Shekhar, and L. Chrostowski, “Ring resonator based polarization diversity WDM receiver”, *Optics Express*, vol. 27, no. 5, pp. 6147-6157, Mar. 2019 (**Editor’s Pick**). [PDF]

26. A. El Sayed, A. K. Mishra, A. Ahmed, A. H. M. Shirazi, S.-P. Woo, Y.-S. Choi, S. Mirabbasi, and S. Shekhar, “A Hilbert-transform equalizer enabling 80 MHz RF self-interference cancellation for full-duplex receivers”, *IEEE Trans. Circuits and Systems – I*, vol. 66, no. 3, pp. 1153-1165, Mar. 2019.

25. H. Jayatilleka, H. Shoman, L. Chrostowski, and S. Shekhar, “Photoconductive heaters enable control of large-scale silicon photonic ring resonator circuits”, *Optica*, vol. 6, pp. 84–91, Jan. 2019. [PDF]

24. A. Sharkia, S. Aniruddhan, S. Mirabbasi, and S. Shekhar, “A compact, voltage-mode type-I PLL with gain-boosted saturated PFD and synchronous peak tracking loop filter”, *IEEE Trans. Circuits and Systems – I*, vol. 66, no. 1, pp. 43-53, Jan. 2019.

23. A. Sharkia, S. Mirabbasi, and S. Shekhar, “A type-I sub-sampling PLL with a 100×100 μm2 footprint and -255 dB FOM”, *IEEE J. Solid-State Circuits*, vol. 53, no. 12, pp. 3553-3564, Dec. 2018 (invited).

22. A. N. Tait, H. Jayatilleka, T. F. De Lima, P. Y. Ma, M. A. Nahmias, B. J. Shastri, S. Shekhar, L. Chrostowski, P. R. Prucnal, “Feedback control for microring weight banks”, *Optics Express*, vol. 26, no. 20, pp. 26422-26443, Oct. 2018. [PDF]

21. A. Nikpaik, A. H. M. Shirazi, A. Nabavi, S. Mirabbasi, and S. Shekhar, “A 219-to-231 GHz frequency-multiplier-based VCO with ~3% peak DC-to-RF efficiency in 65-nm CMOS”, *IEEE J. Solid-State Circuits*, vol. 53, no. 2, pp. 389-403, Feb. 2018.

20. H. Jayatilleka, H. Shoman, R. Boeck, N. A. F. Jaeger, L. Chrostowski, and S. Shekhar, “Automatic configuration and wavelength locking of coupled silicon ring resonators”, *IEEE J. Lightwave Tech.*, vol. 36, pp. 210–218, Jan. 2018 (invited).

19. G. Prasad, L. Lampe, and S. Shekhar, “Digitally controlled analog cancellation for full-duplex broadband power line communications”, *IEEE Trans. Comm.*, vol. 65, no. 10, pp. 4419-4432, Oct. 2017. [PDF]

18. A. H. Ahmed, A. Sharkia, B. Casper, S. Mirabbasi, and S. Shekhar, “Silicon-photonics microring links for datacenters – challenges and opportunities”, *IEEE J. Selected Topics Quantum Elec.*, vol. 22, Nov./Dec. 2016.

17. M. Bahadori, S. Rumley, H. Jayatilleka, K. Murray, N. A. F. Jaeger, L. Chrostowski, S. Shekhar, and K. Bergman, “Crosstalk penalty in microring-based silicon photonic interconnect systems”, *IEEE J. Lightwave Tech.*, vol. 34, pp. 4043–4052, Sep. 2016.

16. G. Prasad, L. Lampe, and S. Shekhar, “In-band full duplex broadband power line communications”, *IEEE Trans. Comm.*, vol. 64, no. 9, pp. 3915-3931, Sep. 2016. [PDF]

15. H. Jayatilleka, K. Murray, M. Caverley, N. A. F. Jaeger, L. Chrostowski, and S. Shekhar, “Crosstalk in SOI microring resonator-based filters”, *IEEE J. Lightwave Tech.*, vol. 34, no. 12, pp. 2886-2897, June 2016 (invited)

14. A. H. M. Shirazi, A. Nikpaik, R. Molavi, S. Lightbody, H. Djahanshahi, M. Taghivand, S. Mirabbasi, and S. Shekhar, “On the design of mm-wave self-mixing-VCO architecture for high tuning range and low phase-noise”, *IEEE J. Solid-State Circuits*, vol. 51, pp. 1210-1222, May 2016 (invited) [PDF]

13. H. Jayatilleka, K. Murray, M. Guillen-Torres, M. Caverley, R. Hu, N. A. F. Jaeger, L. Chrostowski, and S. Shekhar, “Wavelength tuning and stabilization of microring-based filters using silicon in-resonator photoconductive heaters”, *Optics Express*, vol. 23, issue 19, pp. 25084-25097, Sep. 2015. [PDF]

12. T. Musah, J. Jaussi, G. Balamurugan, S. Hyvonen, T.-C. Hsueh, G. Keskin, S. Shekhar, J. Kennedy, S. Sen, R. Inti, M. Mansuri, M. Leddige, B. Horine, C. Roberts, R. Mooney, and B. Casper, “A 4-32 Gb/s bidirectional link with 3-tap FFE/6-tap DFE and collaborative CDR in 22 nm CMOS,” *IEEE J. Solid-State Circuits*, vol. 49, pp. 3079-3090, Dec. 2014 (invited)

11. M. Mansuri, J. E. Jaussi, J. T. Kennedy, T-C. Hsueh, S. Shekhar, G. Balamurugan, F. O’Mahony, C. Roberts, R. Mooney, and B. Casper, “A scalable 0.128-to-1Tb/s 0.8-to-2.6pJ/b 64-lane parallel I/O in 32nm CMOS,” *IEEE J. Solid-State Circuits*, vol. 48, pp. 3229-3242, Dec. 2013 (invited)

10. S. Shekhar, D. Gangopadhyay, E.C. Woo, and D.J. Allstot, “A 2.4GHz extended-range type-I sigma-delta fractional-N synthesizer with 1.8MHz loop bandwidth and -110dBc/Hz phase noise,” *IEEE Trans. On Circuits and Systems – II*, vol. 58, no. 8, pp. 472-476, Aug. 2011

9. S. Aniruddhan, S. Shekhar, and D. J. Allstot, “A CMOS 1.6 GHz dual-loop PLL with fourth-harmonic mixing,” *IEEE Trans. On Circuits and Systems – I*, vol. 58, no. 5, pp. 860-867, May 2011

8. F. O’Mahony, J.E. Jaussi, J. Kennedy, G. Balamurugan, M. Mansuri, C. Roberts, S. Shekhar, R. Mooney and B. Casper, “A 47x10Gb/s 1.4mW/Gb/s parallel interface in 45nm CMOS,” *IEEE J. Solid-State Circuits*, vol. 45, no. 12, pp. 2828-2837, Dec. 2010 (invited)

7. S. Shekhar, M. Mansuri, F. O’Mahony, G. Balamurugan, J. E. Jaussi, J. Kennedy, D. J. Allstot, R. Mooney, and B. Casper, “Strong injection locking in low-Q LC oscillators: modeling and application in a forwarded-clock I/O receiver,” *IEEE Trans. On Circuits and Systems – I*, vol. 56, no. 8, pp. 1818-1829, Aug. 2009 (invited) **(Winner Darlington Best Paper Award 2010)**

6. J. Walling, S. Shekhar, and D. Allstot, “Wideband CMOS amplifier design: time-domain considerations,” *IEEE Trans. On Circuits and Systems – I*, vol. 55, no. 7, pp. 1781-1793, Aug. 2008. [PDF]

5. S. Shekhar, J. Walling, S. Aniruddhan and D. Allstot, “CMOS VCO and LNA using tuned-input tuned-output circuits,” *IEEE J. Solid-State Circuits*, vol. 43, no. 5, pp. 1177-1186, May 2008 (invited). [PDF]

4. S. Shekhar, J. Walling, and D. Allstot, “Bandwidth extension techniques for CMOS amplifiers,” *IEEE J. Solid-State Circuits*, vol. 41, no. 11, pp. 2424-2439, Nov. 2006. (Listed as #4 among the most-read articles of J. Solid-State Circuits in 2006) (http://sscs.org/jssc/hotreads06.htm). [PDF]

3. X. Li, S. Shekhar, and D. Allstot, “gm–boosted common gate LNA and cross-coupled Colpitts VCO/QVCO in 0.18um CMOS,” *IEEE J. Solid-State Circuits*, vol. 40, no. 12, pp. 2609-2619, Dec. 2005

2. W. Zhuo, X. Li, S. Shekhar, S.H.K. Embabi, J.P.D. Gyvez, D. Allstot, and E. Sanchez-Sinencio, “A capacitor cross-coupled common-gate low noise amplifier,” *IEEE Trans. On Circuits and Systems – II*, vol. 52, no. 12, pp. 875-879, Dec. 2005

1. D. Allstot, S. Aniruddhan, M. Chu, J. Paramesh, and S. Shekhar, “Recent advances and design trends in CMOS radio frequency integrated circuits,” *International J. High Speed Electronics and Systems*, vol. 15, no. 2, pp. 377-428, June 2005 (invited)

**Conference**

65. *D. Allstot2, X. Li, and S. Shekhar, “Design considerations for CMOS low noise amplifiers,” IEEE Radio Frequency IC Symposium, Fort Worth, TX, June 2004, pp. 97-100 (Invited) (Listed as #2 among the most-cited articles of RFIC Symposium).

64. M. Chu, S. Shekhar, D. Allstot2, and T.K. Bhattacharyya3, “Design considerations for anti-phase injected quadrature voltage controlled oscillators,” IEEE International Conference on Electronics, Circuits and Systems, Tel Aviv, Israel, Dec. 2004, pp. 25-28.

63. *X. Li, S. Shekhar, and D. Allstot2, “Low power gm–boosted LNA and VCO circuits in 0.18um CMOS,” IEEE International Solid-State Circuits Conference, San Francisco, CA, Feb. 2005, pp. 534-535.

62. *D. Allstot2, S. Aniruddhan, G. Banerjee, M. Chu, X. Li, J. Paramesh, S. Shekhar, and K. Soumyanath, “Circuit techniques for CMOS multiple-antenna transceivers,” IEEE Radio Frequency IC Symposium, Anaheim, CA, June 2005, pp. 225-228 (Invited).

61. S. Aniruddhan, S. Shekhar, and D. Allstot2, “A delay generation technique for fast-locking frequency synthesizers,” IEEE International Symposium on Circuits and Systems, Kos, Greece, May 2006, pp. 5463-5466.

60. S. Shekhar, S. Aniruddhan, and D. Allstot2, “A fully-differential CMOS Clapp VCO for IEEE 802.11a applications,” IEEE International Symposium on Circuits and Systems, Kos, Greece, May 2006, pp. 3241-3244.

59. D. Allstot2, C. Charles, D. Ozis, S. Shekhar, and J. Walling, “RF CMOS design: Living with the substrate,” IEEE International Microwave Symposium Workshop: Substrate Effects in Si RFIC Interconnects, San Francisco, CA, June 2006, pp. 48-66 (Invited)

58. *S. Shekhar, X. Li, and D. Allstot2, “A CMOS 3.1-10.6GHz UWB LNA employing stagger-compensated series peaking,” IEEE Radio Frequency IC Symposium, San Francisco, CA, June 2006, pp. 63-66.

57. D. Allstot2, C.T. Charles, S. Kodali, X. Li, D. Ozis, J. Paramesh, S. Shekhar and J.S. Walling, “CMOS integrated transformers: coming of age,” IEEE International Conference on Solid-State and Integrated- Circuit Technology, Shanghai, China, Oct. 2006, pp. 1480-1483 (Invited).

56. *J. Walling, S. Shekhar and D. Allstot2, “A gm-boosted current reuse LNA in 0.18um CMOS,” IEEE Radio Frequency IC Symposium, Honolulu, HI, June 2007, pp. 613-616.

55. *S. Shekhar, S. Aniruddhan, and D. Allstot2, “A tuned-input tuned-output VCO in 0.18um CMOS,” IEEE Radio Frequency IC Symposium, Honolulu, HI, June 2007, pp. 607-610.

54. D.J. Allstot2, S. Aniruddhan, M. Chu, N.M. Neihart, D. Ozis, S. Shekhar, and J.S. Walling, “Low phase noise CMOS voltage-controlled oscillators,” International Conference on ASIC, Guilin, China, Oct. 2007, pp. 297-302 (Invited).

53. *F. O’Mahony, S. Shekhar, M. Mansuri, G. Balamurugan, J.E. Jaussi, J. Kennedy, B. Casper1, D. Allstot, and R. Mooney, “A 27Gb/s forwarded-clock I/O receiver using an injection-locked LC-DCO in 45nm CMOS,” IEEE International Solid-State Circuits Conference, San Francisco, CA, Feb. 2008, pp. 452-453.

52. *M. Mansuri, F. O’Mahony, G. Balamurugan, J. Jaussi, J. Kennedy, S. Shekhar, R. Mooney, and B. Casper1, “Strong injection locking of low-Q LC oscillators,” IEEE Custom Integrated Circuits Conference, San Jose, CA, Sep. 2008, pp. 699-702.

51. F. O’Mahony, G. Balamurugan, J.E. Jaussi, J. Kennedy, M. Mansuri, S. Shekhar, and B. Casper1, “The future of electrical I/O for microprocessors,” IEEE International Symposium on VLSI Design, Automation & Test, Hsinchu, Taiwan, Apr. 2009, pp. 31-34.

49. A. Masnadi, M. Mahani, H.M. Lavasani, S. Mirabbasi, S. Shekhar, R. Zavari, and H. Djahanshahi, “A Compact Dual-Core 26.1-to-29.9 GHz Coupled-CMOS LC-VCO with Implicit Common-Mode Resonance and FoM of-191 dBc/Hz at 10MHz ”, *IEEE Custom Integrated Circuits Conference*, Boston, MA, Mar. 2020, pp. 1-4.

48. A. Afifi, M. Hammood, N. Jaeger, S. Shekhar, J. Young, and L. Chrostowski, “Cost-effective, Contra-directional couplers as pump rejection and recycling filters for on-chip photon-pair sources ”, *IEEE International Conference on Group IV Photonics (GFP)*, San Jose, CA, Aug. 2019, pp. 1-2.

47. L. Dias, E. Luan, H. Shoman, H. Jayatilleka, S. Shekhar, L. Chrostowski, and N. Jaeger, “Cost-effective, CMOS-compatible, label-free biosensors using doped silicon detectors and a broadband source ”, *OSA IEEE Conference on Lasers and Electro-Optics*, San Jose, CA, May. 2019, pp. ATu4K.5.

46. A. H. Ahmed, D. Lim, A. Elmoznine, Y. Ma, T. Huynh, C. Williams, L. Vera, Y. Liu, R. Shi, M. Streshinsky, A. Novack, R. Ding, R. Younce, R. Sukkar, J. Roman, M. Hochberg, S. Shekhar, and A. Rylyakov, “A 6V swing 3.6% THD >40GHz driver with 4.5× bandwidth extension for a 272Gb/s dual-polarization 16-QAM silicon photonic transmitter ”, *IEEE International Solid State Circuits Conference*, San Francisco, CA, Feb. 2019, pp. 484-486.

45. S. Lightbody, A. H. M. Shirazi, H. Djahanshahi, R. Zavari, S. Mirabbasi, and S. Shekhar, “A −195 dBc/Hz FoMT 20.8-to-28-GHz LC VCO with transformer-enhanced 30% tuning range in 65-nm CMOS”, *IEEE Radio Frequency IC Symposium*, Philadelphia, PA, June 2018 **(Best Student Paper Award Nominee)**.

44. H. Shoman, H. Jayatilleka, A. H. K. Park, N. Jaeger, S. Shekhar, and L. Chrostowski, “Compact silicon microring modulator with tunable extinction ratio and wide FSR”, *IEEE Optical Fiber Communications Conference and Exhibition*, San Diego, CA, Mar. 2018, pp. Tu2E.1

43. A. Sharkia, S. Mirabbasi, and S. Shekhar, “A 0.01mm² 4.6-to-5.6GHz sub-sampling Type-I frequency synthesizer with -254dB FoM”, *IEEE International Solid State Circuits Conference*, San Francisco, CA, Feb. 2018

42. A. El Sayed, A. Ahmed, A. K. Mishra, A. H. M. Shirazi, S-P. Woo, Y-S. Choi, S. Mirabbasi, and S. Shekhar, “A full-duplex receiver with 80MHz bandwidth self-interference cancellation circuit using baseband Hilbert transform equalization”, *IEEE Radio Frequency IC Symposium*, Honolulu, HI, June 2017, pp. 360-363.

41. H. A. Ardakani, A. H. M. Shirazi, S. Shekhar, and S. Mirabbasi, “A low-power temperature sensing system for implantable biomedical applications”, *IEEE NEWCAS Conference*, Strasbourg, France, June 2017, pp. 377-380 (invited).

40. A. H. K. Park, A. S. Ramani, L. Chrostowski, and S. Shekhar, “Comparison of DAC-less PAM4 modulation in segmented ring resonator an dual cascaded ring resonator”, *IEEE Optical Interconnects Conference*, Santa Fe, NM, June 2017, pp. 7-8.

39. G. Prasad, L. Lampe, and S. Shekhar, “Analog interference cancellation for full-duplex broadband power line communications,” *IEEE International Symposium on Power Line Communications*, Madrid, Spain, Apr. 2017, pp. 1-6.

38. H. Jayatilleka, R. Boeck, M. AlTaha, J. Flueckiger, N. A. F. Jaeger, S. Shekhar, and L. Chrostowski, “Automatic tuning and temperature stabilization of high-order silicon vernier microring filters”, *IEEE Optical Fiber Communications Conference and Exhibition*, Los Angeles, CA, Mar. 2017, pp. Th1G.4 **(Top Scored)**

37. S. Shekhar, L. Chrostowski, S. Mirabbasi, S. Nayak, M. AlTaha, A. Naguib, A. S. Ramani, and H. Jayatilleka, “Silicon electronics-photonics integrated circuits for datacenters”, *IEEE Compound Semiconductor IC Symposium*, Austin, TX, Nov. 2016, pp. 1-4 (invited)

36. H. Jayatilleka, R. Boeck, J. Flueckiger, S. Shekhar, N. A. F. Jaeger, and L. Chrostowski, “Silicon photonic in-resonator photoconductive heaters for wavelength”, *Integrated Photonics Research, Silicon and Nano-Photonics (IPR) Conference*, Vancouver, BC, July 2016, (invited)

35. A. H. M. Shirazi, A. Nikpaik, S. Mirabbasi, and S. Shekhar, “A quad-core-coupled triple-push 295-to-301 GHz source with 1.25 mW peak output power in 65nm CMOS using slow-wave effect”, *IEEE Radio Frequency IC Symposium*, San Francisco, CA, May 2016, pp. 190-193.

34. H. Jayatilleka, R. Boeck, J. Flueckiger, S. Shekhar, N. A. F. Jaeger, and L. Chrostowski, “Electronic control and stabilization of silicon photonic microring resonator circuits”, *IEEE European Conference on Integrated Optics*, Warsaw, Poland, May 2016, (invited)

33. M. W. Altaha, S. Nayak, H. Jayatilleka, S. Shekhar, and S. Mirabbasi, “Silicon-photonic devices: electronic control and stabilization,” *IEEE Canadian Conference on Electrical and Computer Engineering*, Vancouver, Canada, May 2016 (invited)

32. H. Jayatilleka, R. Boeck, K. Murray, J. Flueckiger, L. Chrostowski, N. A. F. Jaeger, and S. Shekhar, “Automatic wavelength tuning of series-coupled Vernier racetrack resonators on SOI”, *IEEE Optical Fiber Communications Conference and Exhibition*, Anaheim, CA, Mar. 2016, pp. Th3J.5

31. G. Prasad, L. Lampe, and S. Shekhar, “Enhancing transmission efficiency of broadband PLC systems with in-band full duplexing,” *IEEE International Symposium on Power Line Communications*, Bottrop, Germany, Mar. 2016, pp. 46-51

30. A. Sharkia, S. Aniruddhan, S. Shekhar, and S. Mirabbasi, “A high-performance, yet simple to design, digital-friendly Type-I PLL”, *IEEE Custom Integrated Circuits Conference*, San Jose, CA, Sep. 2015, pp. 1-4

29. A Nikpaik, A. Nabavi, A. H. M. Shirazi, S. Shekhar, and S. Mirabbasi, “A dual-tank LC VCO topology approaching towards the maximum thermodynamically-achievable FoM”, *IEEE Custom Integrated Circuits Conference*, San Jose, CA, Sep. 2015, pp. 1-4

28. H. Jayatilleka, K. Murray, M. Caverley, N. A. F. Jaeger, S. Shekhar, and L. Chrostowski, “Intraband crosstalk of SOI microring resonator-based optical add-drop multiplexers”, *IEEE International Conference on Group IV Photonics*, Vancouver, Canada, Aug. 2015, pp. 3-4

27. N. Eid, H. Jayatilleka, M. Caverley, S. Shekhar, N. A. F. Jaeger, and L. Chrostowski, “Wide FSR silicon-on-insulator microring resonator with bent couplers”, *IEEE International Conference on Group IV Photonics*, Vancouver, Canada, Aug. 2015, pp. 96-97

26. S. Shekhar, R. Inti, J. E. Jaussi, T-C. Hsueh, and B. Casper, “A 1.2-5Gb/s 1.4-2pJ/b serial link in 22nm CMOS with a direct data-sequencing blind oversampling CDR”, *IEEE VLSI Circuits Symposium*, Kyoto, Japan, June 2015, pp. 350-351

25. R. Inti, S. Shekhar, G. Balamurugan, J. Jaussi, C. Roberts, T-C. Hsueh, and B. Casper, “A 0.5-to-0.75V, 3-to-8 Gbps/lane, 385-to-790 fJ/b, bi-directional, quad-lane forwarded-clock transceiver in 22nm CMOS”, *IEEE VLSI Circuits Symposium*, Kyoto, Japan, June 2015, pp. 346-347

24. A. H. M. Shirazi, A. Nikpaik, R. Molavi, S. Mirabbasi, and S. Shekhar, “A class-C self-mixing-VCO architecture with high tuning range and low phase-noise for mm-Wave applications”, *IEEE Radio Frequency IC Symposium*, Phoenix, AZ, May 2015, pp. 107-110 **(Winner 3rd Best Student Paper Award)**

23. H. Jayatilleka, M. Caverley, N. A. F. Jaeger, S. Shekhar, and L. Chrostowski, “Crosstalk limitations of microring-resonator based WDM demultiplexers on SOI”, *IEEE Optical Interconnect Conference*, San Diego, CA, Apr. 2015, pp. 48-49

22. J. E. Jaussi, G. Balamurugan, S. Hyvonen, T-C. Hsueh, T. Musah, G. Keskin, S. Shekhar, J. Kennedy, S. Sen, R. Inti, M. Mansuri, M. Leddige, B. Horine, C. Roberts, R. Mooney, and B. Casper, “A 205mW 32Gb/s 3-tap FFE/6-tap DFE Bi-directional serial link in 22nm CMOS”, *IEEE International Solid State Circuits Conference*, San Francisco, CA, Feb. 2014, pp. 440-441

21. T-C. Hsueh, G. Balamurugan, J. Jaussi, S. Hyvonen, J. Kennedy, G. Keskin, T. Musah, S. Shekhar, R. Inti, S. Sen, M. Mansuri, C. Roberts, and B. Casper, “A 25.6Gb/s differential and DDR4/GDDR5 dual-mode transmitter with digital clock-calibration in 22nm CMOS”, *IEEE International Solid State Circuits Conference*, San Francisco, CA, Feb. 2014, pp. 444-445

20. S. Shekhar, J. E. Jaussi, F. O’Mahony, M. Mansuri, and B. Casper, “Design considerations for low-power receiver front-end in high-speed data links”, IEEE Custom Integrated Circuits Conference, San Jose, CA, Sep. 2013, pp. 1-8

19. M. Mansuri, J. E. Jaussi, J. T. Kennedy, T-C. Hsueh, S. Shekhar, G. Balamurugan, F. O’Mahony, C. Roberts, R. Mooney, and B. Casper, “A scalable 0.128-1Tb/s, 0.8-2.6pJ/bit, 64-lane Parallel I/O in 32nm CMOS”, *IEEE International Solid State Circuits Conference*, San Francisco, CA, Feb. 2013, pp. 402-403

18. D. Gangopadhyay, S. Shekhar, J. S. Walling, and D. J. Allstot, “A 1.6 mW 5.4 GHz transformer-feedback gm-boosted current-reuse LNA in 0.18um CMOS,” *IEEE International Symposium on Circuits and Systems*, Paris, France, May 2010, pp. 1635-1638

17. H-C. Hsu, K. Dasgupta, N. M. Neihart, S. Shekhar, J. S. Walling, and D. J. Allstot, “U-shaped slow-wave transmission lines in 0.18um CMOS,” *IEEE International Symposium on Circuits and Systems*, Paris, France, May 2010, pp. 1296-1299

16. F. O’Mahony, J. Kennedy, J.E. Jaussi, G. Balamurugan, M. Mansuri, C. Roberts, S. Shekhar, R. Mooney, and B. Casper, “A 47x10Gb/s 1.4mW/(Gb/s) parallel interface in 45nm CMOS,” *IEEE International Solid-State Circuits Conference*, San Francisco, CA, Feb. 2010, pp. 156-157

15. F. O’Mahony, G. Balamurugan, J.E. Jaussi, J. Kennedy, M. Mansuri, S. Shekhar, and B. Casper, “The future of electrical I/O for microprocessors,” *IEEE International Symposium on VLSI Design*, Automation & Test, Hsinchu, Taiwan, Apr. 2009, pp. 31-34

14. M. Mansuri, F. O’Mahony, G. Balamurugan, J. Jaussi, J. Kennedy, S. Shekhar, R. Mooney, and B. Casper, “Strong injection locking of low-Q LC oscillators,” *IEEE Custom Integrated Circuits Conference*, San Jose, CA, Sep. 2008, pp. 699-702

13. F. O’Mahony, S. Shekhar, M. Mansuri, G. Balamurugan, J.E. Jaussi, J. Kennedy, B. Casper, D. Allstot, and R. Mooney, “A 27Gb/s forwarded-clock I/O receiver using an injection-locked LC-DCO in 45nm CMOS,” *IEEE International Solid-State Circuits Conference*, San Francisco, CA, Feb. 2008, pp. 452-453. [Presentation Slides]

12. D.J. Allstot, S. Aniruddhan, M. Chu, N.M. Neihart, D. Ozis, S. Shekhar, and J.S. Walling, “Low phase noise CMOS voltage-controlled oscillators,” *International Conference on ASIC*, Guilin, China, Oct. 2007, pp. 297-302 (Invited)

11. S. Shekhar, S. Aniruddhan, and D. Allstot, “A tuned-input tuned-output VCO in 0.18um CMOS,” *IEEE Radio Frequency IC Symposium*, Honolulu, HI, June 2007, pp. 607-610

10. J. Walling, S. Shekhar and D. Allstot, “A gm-boosted current reuse LNA in 0.18um CMOS,” *IEEE Radio Frequency IC Symposium*, Honolulu, HI, June 2007, pp. 613-616. [PDF]

9. D. Allstot, C.T. Charles, S. Kodali, X. Li, D. Ozis, J. Paramesh, S. Shekhar and J.S. Walling, “CMOS integrated transformers: coming of age,” *IEEE International Conference on Solid-State and Integrated-Circuit Technology*, Shanghai, China, Oct. 2006, pp. 1480-1483 (Invited)

8. S. Shekhar, X. Li, and D. Allstot, “A CMOS 3.1-10.6GHz UWB LNA employing stagger-compensated series peaking,” *IEEE Radio Frequency IC Symposium*, San Francisco, CA, June 2006, pp. 63-66

7. D. Allstot, C. Charles, D. Ozis, S. Shekhar, and J. Walling, “RF CMOS design: Living with the substrate,” *IEEE International Microwave Symposium Workshop: Substrate Effects in Si RFIC Interconnects*, San Francisco, CA, June 2006, pp. 48-66 (Invited)

6. S. Shekhar, S. Aniruddhan, and D. Allstot, “A fully-differential CMOS Clapp VCO for IEEE 802.11a applications,” *IEEE International Symposium on Circuits and Systems*, Kos, Greece, May 2006, pp. 3241-3244

5. S. Aniruddhan, S. Shekhar, and D. Allstot, “A delay generation technique for fast-locking frequency synthesizers,” *IEEE International Symposium on Circuits and Systems*, Kos, Greece, May 2006, pp. 5463-5466

4. D. Allstot, S. Aniruddhan, G. Banerjee, M. Chu, X. Li, J. Paramesh, S. Shekhar, and K. Soumyanath, “Circuit techniques for CMOS multiple-antenna transceivers,” *IEEE Radio Frequency IC Symposium*, Anaheim, CA, June 2005, pp. 225-228

3. X. Li, S. Shekhar, and D. Allstot, “Low power gm–boosted LNA and VCO circuits in 0.18um CMOS,” *IEEE International Solid-State Circuits Conference*, San Francisco, CA, Feb. 2005, pp. 534-535 [Presentation Slides (Zip)]

2. M. Chu, S. Shekhar, D. Allstot, and T.K. Bhattacharyya, “Design considerations for anti-phase injected quadrature voltage controlled oscillators,” *IEEE International Conference on Electronics, Circuits and Systems*, Tel Aviv, Israel, Dec. 2004, pp. 25-28

1. D. Allstot, X. Li, and S. Shekhar, “Design considerations for CMOS low noise amplifiers,” *IEEE Radio Frequency IC Symposium*, Fort Worth, TX, June 2004, pp. 97-100. [PDF]

## Dissertations

A. Masnadi, “Radio Frequency CMOS: From Ultrahigh Speed to Ultra-Low Power,” PhD Thesis, Univ. British Columbia, 2018

H. Jayatilleka, “Enabling Practical Deployment of Silicon Ring Resonator-Based Systems,” PhD Thesis, Univ. British Columbia, 2017

S. Lightbody, “Transformer-enhanced High-performance CMOS Voltage-controlled Oscillators,” MASc Thesis, Univ. British Columbia, 2018

C. Yuan, “Design and Analysis of Supply-Noise-Insensitive All-Digital Phase-Locked Loops,” MASc Thesis, Univ. British Columbia, 2017

A. Ramani, “A Differential Push-pull voltage mode driver for vertical-cavity surface emitting laser,” MASc Thesis, Univ. British Columbia, 2017

M. AlTaha, “Automatic Tuning Circuits for Mach-Zehnder Interferometer Optical Switches,” MASc Thesis, Univ. British Columbia, 2017

S. Nayak, “A Fully-Integrated Complementary Metal-Oxide-Semiconductor Receiver with Avalanche Photodetector,” MASc Thesis, Univ. British Columbia, 2017

A. El Sayed, “A Broadband Self-Interference Cancellation Circuit for Simultaneous Full-Duplex Radio Applications,” MASc Thesis, Univ. British Columbia, 2016

A. Sharkia, “On the Design of Type-I Integer-N Phase-Locked Loops,” MASc Thesis, Univ. British Columbia, 2015

S. Shekhar, “Wideband Frequency Synthesizers,” Ph.D. Dissertation, Univ. Washington, 2008

S. Shekhar, “Bandwidth Extension Techniques: Theory and Applications,” MS Thesis, Univ. Washington, 2005

**Book Chapters**

1. D.J. Allstot, S. Shekhar and J.S. Walling, “Design of wideband amplifiers in CMOS,” in Circuits for Emerging Technologies: CMOS and Beyond, K. Iniewski, Editor, CRC Press, 2008

2. D.J. Allstot, S. Aniruddhan, M. Chu, J. Paramesh, and S. Shekhar, “Recent advances and design trends in CMOS radio frequency integrated circuits,” in Design of High Speed Communication Circuits, R. Harjani, Editor, World Scientific Publishing Company, Jan. 2006. ISBN 981-256-590-6

**Patents **

7. S. Shekhar, H. Md Nazmul, and B. Dinesh. “Apparatus for electromagnetic wave manipulation”, *U.S. Patent Application, *17/489,621, 2022.

6. L. Chrostowski, N. A. Jaeger, S. Shekhar, H. Jayatilleka, and H. A. S. Shoman*, *“Method and circuit for reflection cancellation”, U.S. Patent Application No. 17/352,066, 2021.

5. S. Shekhar and A. EI. Sayed, “Integrated circuit for self-interference cancellation and method of performing full-duplex radio communication”, U.S. Patent Application No. 16/892,419, 2020.

4. S. Gupta, E. Shekhar, S. Shekhar, S. Venkatasubramanian, and A. S. Ramani, “Spatial interference cancellation for simultaneous wireless and information power transfer”, U.S. Patent 10,804,988, 2020.

3. S. Shekhar and A. EI. Sayed, “Integrated circuit for self-interference cancellation and method of performing full-duplex radio communication”*, *U.S. Patent 10,680,673, 2020.

2. J. Kulkarni, A. Ravi, D. Somasekhar, G. Balamurugan, S. Shekhar, T. Musah and T-C. Hsueh, “Digitally trimmable integrated resistors including resistive memory elements”, US. Patent 9589615, Mar. 2017.

1. M. Mansuri, S. Shekhar, B.K. Casper and F.P. O’mahony, “Injection locked LC VCO clock deskewing,” US. Patent 7683729, Mar. 2010.